Latch clock signal [5K]The 74(HCT)4040 12-bit counter was used in the prototype. Two devices can be cascaded to make a 24-bit counter (of which we only need 18 bits). However the extra "bit" can be used to generate the necessary latch signal for the EPROM's data latch.

However, one problem is that these counters are ripple counters. Each counter bit is clocked by the preceeding counter bit; the reult of this is that the counter output bits do not increment at the same time, each bit occuring slightly later than the previous giving rise to spurious address generation. A better choice may be to use the 74ACT4520 which contains two 4-bit counters that are not of the "ripple" design. However three of these I.C.'s would be required.

Unfortunately, the EPROM data does not entirely fill the EPROM. Therefore it will be necessary to reset the counters to zero at some address (the 239,842th location actually). In order to achieve this we utilise bit 2 of the EPROM data when a command is being output (EPROM data bit 7 is high). This can be achieved using an AND gate or, in this case, a NAND gate followed by an invertor.

Modified reset circuit [7K] PROBLEM : If we use the output latch data to generate the reset signal, then when the output latch contains the reset code (0x84), the counter is held in reset. Of course, the EPROM outputs the next code (which wont be the reset code any more) but Q0 = 0 (in previous diagram), hence no clock pulse will reach the latch, so the latch never updates -> permanent reset. Thus the initial design was modified as shown opposite where the non-latched "reset" bit was combined with the latched "control". However this led to spurious resets due to the previously described delays in the counter bits.

2nd Reset Modification [8K]Thus the final circuit was changed so that the latched reset signals were used but this time mixing them with the master clock thus ensuring that the stuck-in-reset did not occur.

Next Page : The Master Clock

Page copyright
J.Evans 2002
Last updated
27th July 2002